1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory of a DYNAMIC RANDOM ACCESS MEMORY (hereinafter abbreviated to as DRAM) having a plurality of storage capacity cells.
2. Description of the Prior Art
The bit capacity of DRAMs leading the higher integration race have experience a four-fold growth in the last three years. Presently 256 Kb (Kilobits) DRAMs and 1 Mb (Megabits) DRAMs are mainly being produced, and 4 Mb DRAMs are under development. It is expected that still larger capacity DRAMs, such as 16 Mb and 64 Mb DRAMs, will be developed in the near future. In the DRAMs currently being produced, one bit is stored in a memory cell having a single transistor (pass transistor) and a single capacitor. One cell of the 4 Mb DRAMs currently under development has an area of about 10 .mu.m.sup.2. With the increasing storage capacity, the cell area will gradually diminish to about 5 .mu.m.sup.2 (16 Mb) and then 2.5 .mu.m.sup.2 (64 Mb). In order to prevent radiation induced soft errors, a charge of 200 fc (femtocoulomb) or more must be stored by the capacitor of each cell, so that the capacitance of each cell is maintained at an order of 40 fF (femto-farad).
It is not feasible to hold the above capacitance on the silicon wafer surface alone for 4 Mb DRAMs. Therefore, the capacitor is produced in trenches which have a depth between 2 .mu.m-8 .mu.m in the silicon wafer surface. A variety of DRAM cell structures have been proposed by utilizing such trenches.
Generally the design of DRAM memory cells, as much capacitance as possible should be maintained on the limited surface region without impairing the pass transistor in each cell and the characteristics of the cell-to-cell insulation. As a method for increasing the capacitance, it is theoretically possible to make a thinner dielectric between electrodes, or to employ materials which have a higher dielectric constant, so that the capacitance per unit area may be increased. At present, however, the dielectric suitable for practical use is limited to a SiO.sub.2 film or a SiO.sub.2 /Si.sub.3 N.sub.4 composite film only, and a maximum capacitance can be obtained from a 100 .ANG. thick SiO.sub.2 film from the standpoint of reliability. Accordingly, the capacitance of a capacitor (condenser) per unit area is about 3.5 fF/.mu.m.sup.2. Hence, a capacitor with an electrode area of approximately 11.4 .mu.m.sup.2 is required to maintain the capacitance at 40 fF.
Various cell structures have been proposed to form a capacitor with an electrode area larger than 10 .mu.m.sup.2 in a cell whose surface area is only approximately 10 .mu.m.sup.2.
More specifically, there has been proposed a cell structure which is called a trench transistor cell (TTC.) The TTC includes a capacitor formed in the lower portion of a trench and a vertical pass transistor formed in the upper portion of the trench (see IEEE IEDM: International Electron Devices Meeting, Transactions, p.714, Dec. 1985). The merits for this cell structure are as follows: the cell can dispense with the area necessary for the pass transistor and the bit line contact holes, the cell less affected by the short channel effect or the narrow channel effect of the pass transistor; there is no risk of punching through between the trenches; and the cell is highly tolerant against .alpha.-particle induced soft errors. In contrast the proposed cell structure has the following drawbacks: the cell requires the use of an expensive P/P.sup.+ epitaxial wafer very deep must be formed in the wafer, which results in very complicated manufacturing steps; and the (1/2) Vcc arrangement cannot be adopted which is effective in improving reliability of an insulating film in the capacitor.
There has also been proposed a cell structure which is called BSE (Buried/Storage Electrode Cell) (See IEEE IEDM, Transactions, p.710, Dec. 1985). In this cell structure, a capacitor and a pass transistor are formed in a coplanar surface. Because the BSE structure employs a P/P.sup.+ epitaxial substrate as with the above TTC structure, the BSE structure has the merits of no interaction between the capacitors, and a high tolerance against .alpha.-ray, etc. However, the demerits of the BSE structure are increased costs, and a lack of compatibility with the (1/2) Vcc arrangement, etc. In addition, the BSE manufacturing steps are more simple than the TTC manufacturing steps. Because the area available for the capacitor is very small in the BSE structure, it is expected that BSE will not be adapted for higher integration densities such as 16 Mb and 64 Mb.
Thus, because a P/P.sup.+ epitaxial substrate is used and a P.sup.+ portion of the substrate is utilized as a plate electrode of the capacitor, the TTC and BSE structures do not have an appreciable interaction between the capacitors, and high tolerance against .alpha.-ray, TTC and BSE structures have the demerits of increased cost, and a lack of compatibility with the (1/2) Vcc arrangement, etc. Furthermore, these type of cells are very disadvantageous when the capacitance in the trench is attempted to be increased because the capacitor trench is located at the center of each cell and an isolation region surrounds the outer side of the capacitor trench. Thereby, a structure results in which the circumference of the capacitor trench is shorter than the cell. As required by the subsequent process, the trench must have its side wall inclined to some degree, and the trench becomes V-shaped as a result. With this structure, therefore, the side area of the trench will not be increased even if a deeper trench is formed, and the capacitance cannot be made larger in proportion to the depth of the trench.
For this reason, it is necessary to make the circumference of the trench as long as possible, in order to form a capacitor with the largest practicable capacitance in a limited area. To this end, it is advantageous to form a trench around the cell, and have the cell isolation region and the capacitor region formed inside the trench.
One of these types of cells, a FCC (Folded Capacitor Cell) has been proposed (see IEEE IEDM, Transactions, p.244, Dec. 1984). With this cell structure, although the circumference of the capacitor portion is nearly comparable with the structure of the BSE cell, the trench is V-shaped and this results in the side area of the trench being increased with larger depths. However, problems still exist in the various manufacturing processes such as the cell-to-cell isolating method at the trench bottom, the impurity implanting method to the trench side wall, etc. and achieving in lower tolerances against .alpha.-ray than the BSE structure.
There has also been proposed a cell structure, as shown in FIG. 7, which is called an IVEC (Isolation Merged Vertical Capacitor Cell) (see IEEE IEDM, Transactions, p.240, Dec. 1984). In FIG. 7, trenches 43, 43', 43" are formed to surround memory cell regions 42 and 42' of a silicon substrate 41, and capacitor electrodes 46 and 46' connected to drain regions 45 and 45' of pass transistors via insulating films (SiO.sub.2 films) 44, 44' and 44" are formed in the trenches 43, 43' and 43". The capacitor electrodes (doped polycrystalline silicon) 46 and 46' are also contiguous with the plate electrodes (doped polycrystalline silicon) 48, 48' and 48" via capacitor insulating films (SiO.sub.2 films) 47 and 47'. Designated at 49 and 49' are word lines serving as gate electrodes of the pass transistors, 50 and 50' are source regions of the pass transistors, 51 is an interlayer insulating film, and 52 is a bit line connected to the source regions 50.
This IVEC cell is very effective in increasing the capacitance of the capacitor, because the capacitor is disposed around the cell and has a larger circumference. Also, capacitor separation by the insulating films reduces the interference between the cells. Further, since the capacitor electrodes are isolated from the silicon substrate by the insulating films, tolerance against .alpha.-ray is high. However, with the capacitor electrodes disposed on the side faces of the pass transistors via the insulating films, there is a possibility that a channel may be developed in the side faces of the pass transistors and eventually the pass transistors may leak when the capacitor electrodes are at a higher potential and the bit line is at lower potential. Although the IVEC cell has excellent characteristics as mentioned above, this structure faces inherent problems of leakage of the pass transistors in the course of future developments for the higher integration densities such as 16 Mb and 64 Mb.
It is the object of the present invention to provide a semiconductor memory, such as DRAM, whose individual memory cells include a single capacitor and a single transistor, which can prevent leakage of the transistor even in a memory having a large memory capacity.